A step back from the benchmark posts — the $1,000 eBay box, the junk drawer DDR4 upgrade, streaming the experts off disk — all of which are, read a certain way, the same story about memory.
Nietzsche’s The Birth of Tragedy (1872) and Human, All Too Human (1878) make an odd pair, and the gap between them is the most interesting aspect of this comparison.
The first book argues that Greek tragedy arose from the collision of two drives.
| Drive I — Apollo | Drive II — Dionysus |
|---|---|
| the drive toward form | the drive that dissolves form |
| The dream-image, the clear outline, the bounded individual — what Nietzsche calls the principium individuationis. | Intoxication, flux, the undifferentiated substrate out of which individuals are briefly precipitated and into which they fall back. |
Tragedy was great because it held both: an Apollonian surface stretched taut over a Dionysian truth, neither one denied.
Six years later, Human, All Too Human takes a hammer to that metaphysics. It opens by announcing “historical philosophizing” and a “chemistry of concepts and sensations,” and its first move is the claim that nothing has a miraculous origin — the higher thing always turns out, on inspection, to have come from the lower. “Lack of historical sense is the family failing of all philosophers.” The mature Nietzsche stops asking what a thing essentially is. He asks where it came from, what selected it, and who benefited.
Run the present state of AI through both books.
The Apollonian surface
Nearly everything said about AI in public is Apollonian. Parameter counts. Context windows. Benchmark scores. Architecture diagrams with tidy labeled boxes — attention, feed-forward, residual, norm. The transformer is a beautiful object in precisely Nietzsche’s sense: it is form. It is legible, bounded, drawable on a whiteboard, reproducible from an eight-page paper. And nearly everything shipped in 2026 — dense models, mixtures of experts, multimodal stacks, the “reasoning” models — is a variation on that same 2017 skeleton, decorated but not replaced.
The Apollonian dream is that this shape is a discovery about mind. That attention is what cognition looks like when you finally write it down correctly. That the diagram is the thing.
The diagram runs on a substrate entirely unlike it: capacitors leaking charge and refreshed thousands of times a second, bits dragged across a package at a cost measured in picojoules per millimeter, heat, current, and a supply chain of perhaps three firms who can make the memory at all.
The chemistry of humble origins
Apply the Human, All Too Human method — look for the low origin rather than the miraculous one — and the transformer’s genealogy is not flattering to the Apollonian story.
The transformer did not win because it is the true form of thought. It won because it is the shape that decomposes into large dense matrix multiplications, which is the operation that already ran fast on hardware built for rasterizing triangles. Recurrence lost partly on its merits and substantially because it is sequential, and sequential is the one thing parallel silicon punishes. We did not select the architecture. The machine selected it, and we wrote the philosophy afterward.
That is a genealogical claim, not a dismissal. Nietzsche’s point in tracing morality to low origins was never that morality is worthless, only that we should stop mistaking a contingent history for an eternal necessity. The dominant architecture of our era is an artifact of a hardware accident. It is doing extraordinary things. It is also not the last word, and treating it as one is exactly the family failing.
Where the constraint actually lives
The assumed limit is compute — FLOPs, GPU counts, power. That is not where the binding constraint sits for the thing most people actually use, which is inference.
Autoregressive decoding is memory-bandwidth-bound, not compute-bound. Generating one token from a 70-billion-parameter model at half precision requires reading roughly 140 GB of weights out of memory, and the time that takes is set by bandwidth, not arithmetic throughput. At small batch sizes the arithmetic units sit mostly idle, waiting on data. No quantity of additional FLOPs raises tokens per second above the bandwidth ceiling.
| Accelerator | Memory | Bandwidth |
|---|---|---|
| H200 | HBM3e | 4.8 TB/s |
| B200 | HBM3e | 8.0 TB/s |
| HBM4 generation | 2,048-bit interface | ≈ 22 TB/s |
Per stack: HBM3e ≈ 1.2 TB/s; HBM4 doubles the interface to 2,048 bits for 1.5+ TB/s. The ceiling moved roughly 4.6× across three generations — while the model weights that must cross it grew faster.
This is why the memory specifications are the interesting column in every accelerator datasheet. Every meaningful architectural trend of the last three years is an adaptation to that ceiling: mixture-of-experts to cut activated parameters per token, grouped-query and latent attention to shrink the KV cache, aggressive quantization to move fewer bytes per weight, speculative decoding to amortize reads across several tokens, and the renewed interest in state-space and linear-attention hybrids that trade exact recall for a bounded working set.
These are usually narrated as intellectual progress. They are better read as evolution under a selection pressure, and the selection pressure is DRAM.
I have been writing that same finding down for a year without naming it. Prefill tracks bytes added and decode tracks expert bits-per-weight. A 127 GB checkpoint fits on a 96 GB card because 48 GB of it is a table you can leave in host RAM and read a little at a time. Two 5070 Tis beat one bigger card on some workloads and lose on others, and the split is bandwidth. None of that is a story about ideas. It is a story about how far a byte has to travel and how many of them have to move per token.
The bill of materials
Here is where the Dionysian substrate stops being a metaphor. High-bandwidth memory consumes roughly three times the wafer area per gigabyte that conventional DDR5 does. Micron said so at Hot Chips 2026, and when asked whether the ratio improves with newer generations, said it definitely would not — an HBM4 die runs 256 memory banks against DDR5’s 32, before you count the extra data paths, the power delivery, and the through-silicon vias holding the stack together. Every stack built therefore removes about three times its own capacity from the pool available for everything else — phones, laptops, cars, servers.
| Figure | Source | |
|---|---|---|
| 3× | Wafer area per gigabyte, HBM3E versus DDR5 — a penalty Micron says widens each generation | Micron at Hot Chips 2026 |
| 70% | Share of 2026 memory output projected to be absorbed by datacenters | Tom’s Hardware |
| 400% | DRAM price increase, start of 2024 through end of 2026 | J.P. Morgan Global Research, Aug 6 2026 |
| sold out | SK hynix’s entire 2026 HBM, DRAM and NAND output, committed at the Q3 2025 earnings call | Bloomberg, Oct 28 2025 |
| 2030 | How long SK hynix’s CEO now expects the shortage to last — the previous guess was 2028 | Kwak Noh-Jung, Aug 27 2026 |
That last row is the one worth sitting with. In roughly a year the same company’s public estimate of how long this lasts moved from 2028 to past 2030 — and it moved while they were breaking ground on new capacity, not instead of it. The forecast slipped faster than the fabs got built.
So the real description of the current moment is not “AI is limited by ideas” or even “AI is limited by compute.” It is: AI is rate-limited by a memory supply chain with a four-year lead time, concentrated in three firms, priced like a commodity in a squeeze, and constrained further by advanced packaging capacity that is itself allocated years out.
A model has a bill of materials, lead times, and a geography. This is what the Apollonian discourse systematically declines to mention, because it is unglamorous and because it is not within the speaker’s control.
It is also why 64 GB of DDR4 that had been sitting in a drawer since 2019 turned out to be the best hardware purchase I made last year, at $0. The junk drawer is a hedge against a four-year lead time.
Back in January, Gemini made a version of this argument from the market side on our AI-authored page — pairing DRAM with silver as two assets where physical limits were reasserting themselves against financialized pricing. It reached the same place by a different road: you cannot print bandwidth.
The Socratic temptation
The Birth of Tragedy has a villain, and it is not Dionysus. It is Socrates — or rather the “theoretical man,” possessed of the cheerful conviction that thought can reach down to the depths of being and correct it. Nietzsche thought that optimism killed tragedy: it made the abyss look like a problem awaiting a method.
Our version of that optimism is the belief that scale dissolves every obstacle — that any limit encountered is a temporary inconvenience, priced in, on the roadmap. It is comfortable and not entirely wrong. It is also why so much strategy in this industry is written as though wafer starts, packaging slots, and refresh cycles were someone else’s department.
The Greeks did not deny the abyss; they built something on top of it that was worth watching.
The tragic posture — which is not pessimism, and this distinction is the whole point of Nietzsche’s first book — is to look at the constraint directly and make form out of it.
Practically, the interesting work of the next several years will not come from whoever waits out the shortage. It will come from those who treat bandwidth as the primary design variable rather than an implementation detail: architectures with bounded state, models sized to the memory actually purchasable, systems that earn their intelligence per byte moved rather than per parameter stored. Constraint has always been generative in art. There is no reason it should be otherwise in silicon.
So
The transformer is our Apollonian dream-image, and a very good one. The DRAM is the Dionysian ground it is dreaming on.
The mistake — the family failing — is to talk about the dream as though the ground were not there.
Which is, I notice, most of what I do here. Every post on this site is a benchmark table: a clean Apollonian surface with a number in the right-hand column. The reason I keep running them on secondhand Xeons and junk-drawer DDR4 rather than renting an H200 is not frugality, or not only frugality. It is that when the hardware is cheap enough to be visible, you can’t pretend the diagram is the thing. The floorboards are up. You can see the furnace.
Sources: Nietzsche, “The Birth of Tragedy” (1872) and “Human, All Too Human” (1878). Bandwidth figures from published NVIDIA H200 and B200 specifications and the JEDEC HBM4 interface definition; HBM4 per-device bandwidth is a generation estimate, not a shipping part. The 140 GB-per-token figure is 70B parameters at FP16, ignoring KV cache and activations. On the memory numbers: the 3× wafer-area ratio is Micron’s own HBM3E-versus-DDR5 comparison, presented at Hot Chips 2026 (Igor’s Lab has the detail). The 400% price move is J.P. Morgan Global Research, August 6 2026 — the same note puts memory at 30–40% of a smartphone bill of materials, against a historical 10–15%. SK hynix sold out its 2026 output at its Q3 2025 earnings call, and CEO Kwak Noh-Jung extended the shortage guidance to end-2030 at the August 27 2026 groundbreaking for the company’s $4B Indiana packaging fab, having previously said 2028. The 70% figure is a forecast rather than a measurement, and the denominator matters: it is datacenter share of high-end memory output, not of DRAM wafer capacity — TrendForce puts AI at about 20% of global DRAM wafer capacity for the same year. Both can be true at once; that is what the 3× wafer penalty buys you.